Integrated circuitry is typically fabricated on and within semiconductor substrates, such a bulk monocrystalline silicon wafers. In the context of this document, the term "semiconductive substrate" is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term "substrate" refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
Electrical components fabricated on substrates, and particularly bulk semiconductor wafers, are isolated from adjacent devices by insulating materials, such as insulating oxides. One isolation technique uses trench isolation, whereby trenches are cut into a substrate and are subsequently filled with insulating material, such as undoped silicon dioxide deposited by plasma-enhanced decomposition of tetraethylorthosilicate (PETEOS). The insulating material is typically planarized back to define isolated trenches filled with oxide. A subclass of trench isolation is "shallow trench isolation". In the context of this document, "shallow" shall refer to a distance no greater than about 1 micron from the outermost surface of the substrate material within which the isolation material is received. Also in the context of this document, "substantially undoped" means a layer having a dopant concentration which is less than or equal to 10.sup.18 atoms/cm.sup.3.
An example prior art construction and its associated problems is described with reference to FIGS. 1-3. A wafer fragment 10 includes a bulk silicon substrate 12 having a protective pad oxide layer 14 formed thereover. A trench 16 is cut through oxide layer 16 and into substrate 12. A thermal oxide layer 17 lines trench 16. Such is filled with a deposited oxide material 18, such as oxide formed by PETEOS. Such has been planarized back, and a deposited nitride layer (not shown) selectively stripped relative to deposited oxide 18 and thermally grown oxide 14 to produce the deposited oxide projecting outwardly relative to both substrate 12 and thermal oxide layer 14.
Thermal oxide layer 14 is typically inadequate to function as a gate dielectric layer, and is accordingly removed from the wafer as shown in FIG. 2. FIG. 2 illustrates an oxide etch of layers 18 and 14 effective to outwardly expose substrate 12. An example for such etching is wet etching with HF. To assure complete etching of the oxide layer 14, a degree of over-etch is conducted. Unfortunately, this has the undesired effect of producing recesses or keyholes 20 at interfaces where semiconductive substrate 12 joins with deposited oxide 18. The typical faster etch rate of deposited oxide relative to grown oxide only exacerbates this problem.
Referring to FIG. 3, a gate dielectric layer 22 is thereafter formed (i.e., thermally grown or deposited oxide), followed by deposition and patterning of a conductive layer 24 (i.e., polysilicon capped with WSi.sub.x) to form a desired field effect transistor gate. Unfortunately, this abrupt oxide step or recess 20 apparently results in a parallel low threshold-voltage (V.sub.t) device along the transistor width. The V.sub.t of this edge device also depends on geometric factors, such as the gate wrap-around, corner radius, and sidewall corner angle. Yet, this abrupt oxide step or recess is believed to cause sub-threshold "kink" which adversely affects device reliability and operation.